A prior art memory cell configuration utilizes a single capacitor in combination with three transistors, and may be referred to as a 3T-1C memory cell. Such memory cell is schematically illustrated in FIG. 1 as a memory cell 2. The three transistors are labeled as T1, T2 and T3.
A source/drain region of T1 connects with a write bitline (WBL), and the other source/drain region of T1 connects with the capacitor (CAP). A gate of T1 connects with a write wordline (WWL).
A source/drain region of T2 connects with a common plate (CP), and the other source/drain region of T2 connects with a source/drain region of T3. The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground≤CP≤VCC). In some applications the common plate is at a voltage of about one-half VCC (i.e., about VCC/2).
A gate of T2 connects with the capacitor (CAP).
One of the source/drain regions of T3 is the source/drain region connected with the source/drain region of T2, and the other connects with a read bitline (RBL). A gate of T3 connects with a read wordline (RWL).
The 3T-1C configuration of FIG. 1 may be utilized in DRAM (dynamic random access memory). Presently, DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. A possible advantage of 3T-1C configurations as compared to 1T-1C configurations is that charge stored on the capacitor within the 3T-1C configurations is utilized to control a gate of T2 rather than being directly shared with a bitline. This may enable much lower capacitance to be utilized in the 3T-1C configurations as compared to the 1T-1C configurations. One of the limitations to scalability of present 1T-1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, utilization of 3T-1C configurations, and the associated lower capacitance needs of such configurations, may ultimately enable increased scalability as compared to the 1T-1C configurations. However, the 3T-1C configurations have more components than the 1T-1C configurations (three transistors instead of one), which may make it difficult to incorporate 3T-1C configurations into highly-integrated modern memory architecture.
It would be desirable to develop 3T-1C configurations suitable for incorporation into highly-integrated modern memory architectures.